1. Field of the Invention
This invention relates to memory interface devices and, more particularly, to devices which provide a data and address path between an arithmetic/logic unit and a memory and which provide mechanisms for generating or modifying memory addresses.
2. Description of the Prior Art
In a high-performance processor system, it is desirable to free the high-speed internal data processor from slower memory and peripheral system sections. An interface circuit is needed that provides storage for equipment address and data transfer. Also, for maximum speed, the interface circuit must operate in parallel with other parts of the system and be able to both route data and do memory address operations.
In the past, the arithmetic/logic unit (ALU) of the data processing system was required to perform arithmetic and logic functions in order to generate addresses for accessing the memory unit of the system. During the periods of time when the ALU was performing these system overhead tasks it was unavailable for its primary function of operating on data. In generating memory addresses, it is frequently necessary to perform arithmetic operations for, for example, indexed or base register addressing where an incremental or offset value must be added to an address. In a high-speed system, the use of the main system data processor to perform these functions is wasteful of valuable computing time.
It is an object of the present invention, therefore, to provide an interface unit between the system ALU and the memory unit capable of performing limited arithmetic and logic functions to relieve the system ALU of the burden of generating memory addresses and performing memory or peripheral overhead operations.
It is a further object of the invention to provide a device which is capable of performing limited arithmetic, logical and data path selection operations such that it may be utilized as a system ALU in limited systems.
It is a still further object of the present invention to provide a flexible register structure to handle system address register requirements such as index storage, program counter storage and the like.